1. Field of the Invention
The present invention concerns power-up reset circuits for an integrated circuit and more particularly a power-up reset circuit for use as part of a monolithic integrated circuit.
2. Description of the Prior Art
When power is first applied to a variety of integrated circuits it is often desirable to reset certain circuit elements such as logic flip-flops and memory shift registers to some predetermined initial state. This circuit initialization process is commonly achieved by a power-up reset circuit which supplies an initial reset voltage signal to the various circuit elements for a brief period of time after the circuit is turned on. It is generally desirable for the power-up reset circuit to be formed on the monolithic integrated circuit chip having the circuit elements requiring initialization. However, it is also desirable to have the reset circuit occupy as little space on the chip as possible. In order for the entire integrated circuit to become functional as quickly as possible, it is advantageous to minimize the time during which the reset circuit is active to the briefest period necessary to initialize the various circuit elements. Typically reset signals need only be applied for one to one hundred microseconds.
Although reset signals may be of extremely short duration, integrated circuit power supplies generally require longer periods to begin supplying voltages at levels sufficient for circuit element initialization. In some instances a power supply may require up to ten milliseconds to reach a voltage level sufficient to reset some circuit elements. Thus power-up reset circuits must normally remain on until the power supply has achieved a desired voltage level plus some amount of time necessary to actually reset the various circuit elements.
Conventional power-up reset circuits commonly include a pair of complementary metal oxide semiconductor field effect transistors (CMOS FET's) providing an output which switches between a reset voltage supplied by the power supply and a ground or reference voltage and a resistor/capacitor series bridge for keeping the reset circuit active for a desired time period determined by the time constant of the bridge. This approach, however, suffers from a number of disadvantages. The individual resistive and capacitive elements providing a time delay sufficient to accommodate slow ramping power supplies typically occupy an undesirably large amount of monolithic integrated circuit chip space. This reduces the number of active circuit elements which can be built into the chip. Furthermore, such circuits are generally designed independent of the actual power supply with which they will operate, and proper operation can therefore not be assured. Once a conventional reset circuit is fabricated, the active period of the circuit typically remains fixed. Consequently, inadequate power-up resets my occur with power supplies that take longer to supply sufficient reset voltage levels than the fixed active period of the reset circuit. Alternatively, in situations when power supplies take less time to supply the necessary reset voltage than the predetermined reset circuit active period, the reset circuit elements still do not become fully functional until the reset circuit shuts off. Thus, there is unnecessary delay.
Thus, there exists a need for a power-up reset circuit which may be resident on a chip without taking up an undesirable amount of space and which operates for only a minimum circuit reset period after a power supply has begun supplying voltage sufficient for circuit element reset.